Different structures have been imagined for forming PNP or NPN transistors able to pass relatively high currents in integrated circuits. The present invention relates more particularly to integrated structures comprising vertical NPN transistors able to pass high currents and aims at providing also in such structures PNP transistors able to pass high currents and adapted, if so desired, to satisfactorily control the vertical NPN transistors.
FIG. 1 shows a particular integrated circuit structure comprising above an N.sup.+ type substrate 1 a first P type epitaxied layer 2 and a second weakly doped N type epitaxied layer 3. This structure is relatively unusual for generally integrated circuit wafers comprise a P type substrate carrying an N.sup.- type epitaxied layer, that is to say a structure comprising only the equivalent of layers 2 and 3, layer 2 corresponding in this case to a substrate.
In the left-hand and right-hand parts of FIG. 1 isolated by P.sup.+ type walls reaching the P type layer 2, conventional and well known NPN and PNP transistors have been shown. The regions comprising these transistors bear no numerical reference; only the types of conductivity of the different layers have been shown and the letters E,B and C have been placed opposite the respective emitter, base and collector metalizations.
The advantage of the structure having two epitaxies of opposite types, illustrated in FIG. 1, resides essentially in the fact that it allows high current vertical NPN transistors to be formed such as shown in the central part of the figure. For these NPN transistors, the lower face of the substrate is metalized and corresponds to the collector. Within the N.sup.- type layer 3 is diffused a P type zone 5 corresponding to the base within which is diffused an N type zone 6 corresponding to the emitter. The N.sup.- type layer 3 is connected to N.sup.+ layer 1 by an N.sup.+ buried layer 7. In fact, this layer 7 results from two successive and superposed implantation/diffusions formed respectively in substrate 1 before the epitaxial growth of layer 2, then in layer 2 before the epitaxial growth of layer 3. The advantages of the vertical NPN transistor structure shown appear clearly and reside essentially in the fact that such transistors can pass high currents while presenting low ohmic drops.
Nevertheless, if it is desired to use, in a structure of the kind shown in FIG. 1, a PNP transistor able to pass a high current, for example for controlling a vertical NPN transistor, a conventional lateral structure will have to be used such as shown in the right-hand part of the figure. But, a known defect of lateral PNP transistors formed by conventional technologies resides in their inability to deliver high current intensities (greater than 0.5 mA per element). This leads to multiplying the number of elements, so in taking up a large silicon area.
When too high a current is demanded of a lateral PNP transistor, two principal phenomena occur: on the one hand, the current gain decreases; on the other hand, a high parasite current is diverted towards the negative terminal of the power supply source (the substrate forming a second collector). This diverted current may become considerable (of the same order of size as the useful current) if, in addition, the PNP transistor is in a saturation condition. The result is that the power is taken from the power supply and dissipated in heat in the semi-conductor chip. This power may be high if the circuit is operating at a high voltage.
It may be considered that the PNP transistor is associated with a parasite PNP transistor generally called "substrate PNP transistor" which has the same base as the useful PNP transistor and a collector corresponding to the substrate, that is to say in the case of the structure illustrated in FIG. 1, to layer 2; this parasite transistor has two emitters, one being the emitter and the other the collector of the useful PNP transistor. It is because of this second emitter (the collector of the useful PNP transistor) that the increase of the parasite current is explained in the case of saturation of the useful PNP transistor.
One object of the present invention is to resolve these problems and to provide a PNP transistor structure compatible with the structure shown in FIG. 1 and able to pass high currents without causing parasite currents to appear leading to overheating of the semi-conductor chip.
Another object of the present invention is to provide a particular application of this PNP transistor structure as means for controlling a high current NPN transistor.